This invention concerns a semiconductor device and its manufacturing method and, more in particular, this invention relates to a multi-layered wiring structure formed by using a so-called dual damascene method and a technique effective to application to a semiconductor device having such a multi-layered wiring structure.
The multi-layered wiring technique is essential in the manufacture of semiconductor devices along with improvement in the performance and micro-miniaturization of the size in the semiconductor devices. As a method of forming wiring layers in semiconductor integrated circuits, it has been known a method of depositing a thin film of an aluminum (Al) alloy or a high melting metal such as tungsten (W) on a dielectric film, then forming a resist pattern of an identical shape with that of a wiring pattern on a thin film for wiring by a lithographic step and forming a wirings pattern using the resist pattern as a mask by a dry etching step. However, the method of using the aluminum alloy or the like involves a problem that wiring resistance increases remarkably along with size-reduction of the wirings to increase wiring delay and deteriorate the performance of the semiconductor device. Particularly, in high performance logic LSI (large scale integrated circuits), this performance inhibiting factor gives a significant problem.
In view of the above, it has been studied a so-called a damascene method of burying a wiring metal comprising copper (Cu) as the main conductor layer on a groove formed to a dielectric film and then removing excess metal outside of the groove by using a CMP (Chemical Mechanical Polishing) method thereby forming a wiring pattern in the groove. Particularly, a dual damascene method of forming wiring grooves in which the upper layer wirings are formed and via holes for connecting the upper layer wirings and the lower layer wirings respectively in the dielectric film and then burying a wiring metal into the via hole and the wiring groove simultaneously can reduce the wiring resistance by about 20% and remarkably simplify the manufacturing steps, decrease the cost and attain QTAT (Quick Turn and Around Time), compared with a method of using the aluminum alloy or the like described above.
By the way, for the dielectric film in which the wiring grooves are formed (hereinafter simply referred to as an inter-wiring layer film) and dielectric film in which the via holes are formed (hereinafter simply referred to as an inter via layer film), a laminate structure in which an etching stopper film and a silicon oxide film (SiO2) are deposited successively from the lower layer is proposed. The silicon oxide film comprises a TEOS oxide film deposited, for example, by a plasma CVD (Chemical Vapor Deposition) method using a TEOS (Tetra Ethyl Ortho Silicate: Si(OC2H5)) gas and an ozone (O3) gas. When the dielectric film is constituted of the TEOS oxide film, a silicon nitride (SiN) film usually deposited by a plasma CVD method is used as an etching stopper film.
However, since the specific dielectric constant of the silicon oxide film is about 4 and the specific dielectric constant of the silicon nitride film is about 7, it may be considered that abrupt increase of wiring delay caused by the increase of the wiring capacitance can not be suppressed only by the introduction of the copper wiring in and after the generation where 0.13 xcexcm is a design rule. In view of the above, use of a low dielectric constant material with a specific dielectric constant of about 2 to 3 has been studied for the material constituting the inter-wiring layer film.
By constituting the inter-wiring layer film with a low dielectric constant film, the wiring capacitance can be reduced compared with the constitution with the silicon oxide film. Further, even when relatively thick wirings required for obtaining desired wiring resistance are formed, since the inter-wiring layer film is constituted of the low dielectric constant film, the wiring capacitance between the adjacent wirings in an identical layer can be suppressed relatively lower.
As a method of forming damascene wirings by applying the interlayer dielectric film comprising the low dielectric constant material, several methods have been proposed and an etching process in a case of adopting various dielectric constant materials for the duel damascene wirings is described, for example, in xe2x80x9cmonthly Semiconductor Worldxe2x80x9d, p 74 -p 76, issued from Press Journal, 1998, November.
Further, Japanese Published Unexamined Patent Application Hei 8(1996)-316209 by Tatsumi discloses a method of forming a via hole to a stacked dielectric film of low dielectric constant where a silicon oxide type dielectric film is formed on an organic polymeric dielectric film by patterning a silicon oxide type dielectric film and then plasma etching the organic polymeric dielectric film of the lower layer by an O-type gas using the silicon oxide type dielectric pattern as a mask.
Further, Japanese Published Unexamined Patent Application Hei 9(1997)-306988 by Suzuki et al discloses a method of forming, on a first dielectric film covering lower layer wirings, a second dielectric film of a lower etching rate than that of the first dielectric film, then forming openings to the second dielectric film and then forming a third dielectric film of a higher etching rate than that of the second dielectric film. Subsequently, grooves for exposing the openings are formed to the third dielectric film and forming via holes in the first dielectric film under the openings.
However, when the present inventors have studied on copper dual damascene in which the inter-wiring layer film is constituted of the low dielectric constant film and the inter-via layer film is constituted of a silicon oxide film, it has been found that the following problems are present.
For example, when copper as the connection members in the via hole is thermally expanded by the temperature elevation from room temperature to about 500xc2x0 C., stress is formed in the direction of widening the via hole. However, the silicon oxide film constituting the inter-via layer has a characteristic showing relatively large thermal stress of about 130 MPa and Young""s modulus of about 70 GPa respectively and causing less elastic deformation. Therefore, the silicon oxide film repulses strongly to the stress of copper and, as a result, the silicon oxide film forms a stress in the direction of compressing the copper in the via hole.
Since the stress caused by the expansion of the copper repulses the stress from the silicon oxide film as the inter-via layer film to each other, a portion of the expanded copper in the via hole is absorbed to copper as the wiring member in the wiring groove. When volume shrinkage occurs by temperature lowering, the amount of copper becomes insufficient to fill the inside of the via hole to cause voids in the via hole. This increases the resistance of the connection member in the via hole given with the thermal stress and, further, the life of wirings is deteriorated by electromigration.
This invention intends to provide a technique capable of improving the heat resistance and the electromigration resistance of dual damascene wirings.
The foregoing and other objects and novel features of this invention will become apparent with reference to the description of the specification and the accompanying drawings.
Among the inventions disclosed in this application, outlines for typical one are simply explained as below.
(1) A semiconductor device according to this invention comprises wirings formed in wiring grooves and a connection member formed integrally with the wirings in via holes for connecting the wirings and lower layer wirings thereof in which the Young""s modulus of a first dielectric layer formed with the via holes is relatively smaller than the Young""s modulus of a second dielectric layer formed with wiring grooves.
(2) A method of fabricating a semiconductor device comprising wirings formed in wiring grooves and a connection member formed integrally with the wirings in via holes for connecting the wirings and lower layer wirings thereof in which the Young""s modulus of a first dielectric layer formed with the via holes is relatively smaller than the Young""s modulus of a second dielectric layer formed with wiring grooves, comprises a step of forming a first dielectric layer with a relatively small Young""s module and a second dielectric layer with a relatively large Young""s modulus successively on a substrate, a step of forming via holes at predetermined regions of the first dielectric layer and forming wiring grooves at predetermined regions of a second dielectric layer and burying a conductive member inside the via holes and the wiring grooves.
According to the constitution described above, since the wiring grooves buried with the wirings are surrounded with the second dielectric layer of a relatively large Young""s modulus, and the via holes for connecting the wirings and the lower layer wirings thereof are surrounded with the first dielectric layer of a relatively small Young""s modulus, even when the volume of the connection member formed integrally with the wirings in the via holes is expanded by temperature elevation, the first dielectric layer causes elastic deformation correspondingly and the second dielectric layer functions to suppress the volumic expansion of the wirings, absorption of the connection member in the via holes to the wiring member in the wiring grooves can be suppressed.